Development of cost-effective high-density through-wafer interconnects for 3D microsystems

High-density through-wafer interconnects are of great interest for fabricating real 3D microsystems. A complete solution for realizing through-wafer interconnects is presented. The proposed solution is believed to be cost effective and easy to integrate in a device process flow. A deep reactive ion etch process was developed to etch 20 × 20 µm2 via holes through 300 µm thick silicon wafers. Thermal oxide is used to insulate the vias from the bulk silicon and heavily doped polysilicon is used as the conductor. Aluminum metallization is provided on both sides of the wafer. The electrical resistance of a single through-wafer via is close to 30 Ω.