Sammendrag
Four different flip-flops dimensioned for subthreshold operation have been designed and implemented in layouts.
The four full custom, race-free, D-flip-flops were implemented in
a standard 65 nm CMOS process and verified by measurements,
when used in 2 divide-by-3 circuits. The first frequency divider,
using standard topologies, demonstrated functionality down to a
supply voltage of 132 mV, while the second variant, based on
a recently proposed ”‘slice-based”’ approach, was functional for
a supply voltage down to 137 mV. The frequency divider using
traditional 4-transistor NAND and NOR topologies had lower
energy per operation than the alternative 8-transistor NAND and
NOR implementation. At 0.1 MHz, the figures were about 2.1 fJ
and 3.5 fJ, respectively. For supply voltages from 0.2 to 1.2 V,
a static flip-flop using 8-transistor NOR- gates plus one inverter
had the lowest static power consumption among the 4 flip-flops.
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