Sammendrag
When using standard multi-Vt CMOS processes
when making logic gates, often for example Low-Vt (LVT), or
Standard-Vt (SVT) or High-Vt (HVT) transistors are used within
one and the same basic logic building block, like for example
a NAND or NOR circuit. We show, to the contrary, how a
combination of different types within a single logic circuit may
be exploited to reduce energy consumption and increase robustness towards process variations. Additionaly, Reverse Short
Channel Effects (RSCE) are exploited by using non-minimum
gate lengths for increased robustness agains process variations.
Also, a recently proposed technique using very regular layouts
accompanying the above mentioned techniques in a 16-bit adder
implemented in 65 nm CMOS. Chip measurements using Sub-/Nearthreshold supply voltages demonstrate the functionality of
the adder for a voltage range of 119 mV to 350 mV. Simulations
show that by increasing gate lengths to 200 nm instead of the
minimum 60 nm, may increase the footprint area of logic gates
by only 12%, while at the same time reducing probability of
failure by up to several orders of magnitude. Simultaneously,
energy per operation is reduced, when compared to conventional
design methods using minimum, or relatively short, gate lengths
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