Subthreshold CMOS Cell Library by 22 nm FDSOI Technology

Two different CMOS transistors with a low threshold voltage, given by a commercial available 22 nm FDSOI CMOS technology were investigated and assembled into several libraries of logic gates. The logic gates provided in the cell library should be sufficient to create most digital logic circuits, and are in addition designed to work in the subthreshold region with a supply voltage of 350 mV. Physical layout designs were made for the different digital ports, where parasitic capacitances were then extracted to provide more realistic simulations and performance results. Compared to schematic simulation, layout design and parasitic capacitances proved to reduce speed by a factor of 5 to 10, as well as increasing the transistors’ threshold voltage by 14.6 % for the NMOS, and 32.5 % for the PMOS. The increased threshold voltage thus led to a reduced static power consumption and increased switching energy. The transistor with the lowest threshold voltage showed especially good performance results with respect to low power consumption while still maintaining speed requirements. This transistor is throughout the report referred to as mosfet low. Two cell libraries were made for this transistor, where one applies a forward body-bias of ±2 V while the other have the bulk nodes connected to ground, which gives a 0 V body-bias. The libraries are supplied with schematics and layout designs, and are in addition mapped for performance data such as static power consumption, delay and switching energy consumption for every logic gate. A minimum speed of 40 MHz with a lowest possible power consumption for a 16by12-bit adder, was the aim of the project. Presented in this report is a 16by12-bit Adder built by Ripple-Carry Adders, which were simulated to reach a speed of 44.26 MHz at a supply voltage of VDD=350 mV with 0 V body-bias. Static power and switching energy consumption were simulated to 26.60 µW and 207.95 fJ, respectively.