Transistor Modeling for the VDSM Era

We review the field effect transistor modeling with emphasis on the device parameter extraction for testing. We consider the physics-based Universal Charge Control Model, which allows us to describe the subthreshold, the weak inversion, and the strong inversion regimes in MOSFETs using a relatively small set of parameters, most of which are related to the device structure or fabrication process. This small parameter set makes the task of parameter extraction easier. The model accounts for velocity saturation, finite output conductance in the saturation regime, Drain Induced Barrier Lowering (DIBL), kink effect, floating body effect (for SOI transistors and TFTs), and subthreshold leakage. The model has been applied to n-channel and p-channel silicon MOSFETs, SOI transistors, GaAs MESFETs, AlGaAs/GaAs and AlGaAs/InGaAsn-channel and p-channel HEMTs, a-Si TFTs,poly-Si TFTs,organic TFTs, AlGaN/GaN HEMTs, and to new emerging heterodimensional transistors. For compound semiconductor devices, additional effects, such as frequency dispersion and temperature dependence of model parameters, and gate leakage current, including hot-carrier leakage, have been accounted for. As an example of practical use of advanced FET models, we discuss AIM-Spice, which can be downloaded from the WEB at www.aimspice.com.