Evolving Fault Tolerance on an Unreliable Technology Platform

One of the key areas in which evolvable hardware has been shown to excel is in achieving robust analogue and digital electronics. In this paper this domain is investigated further by manipulation of the digital abstraction. Some of the strict requirements of digital gates are relaxed in order to increase the complexity of the functionality available to evolution in order to evolve fault tolerant designs. Results from extrinsic evolution of a 2-by-2 bit multiplier, based on CMOS technology under various noise and fault conditions, illustrate the suitability of the messy gate methodology used herein for evolution of a fault tolerant design.