STIFF: Thermally Safe Temperature Effect Inversion Aware FinFET based Multi-core

FinFET, a non-planar device, has become the prevalent choice for chip-multiprocessor (CMP) designs due to its lower leakage and improved scalability as compared to planar CMOS devices. FinFETs are fundamentally different from the conventional CMOS circuits in terms of circuit-delay vs. temperature, i.e. circuit-delay decreases in FinFET at higher temperature even in the super threshold supply-voltage regime. Such characteristic of FinFET is known as temperature effect inversion (TEI). But, drastic increase in channel temperature of FinFET may lead to increase in leakage consumption and may accelerate the circuit aging process due to self heating effect (SHE). This paper introduces STIFF, that balances the upsides of TEI against the potential hazardous SHE in a FinFET based CMP. Basically, STIFF exploits online performance statistics to determine the thermal intensity of the cores and local-caches, and scales supply-voltage prudentially to maintain a stable core frequency and local-cache performance on-the-fly by exploiting TEI, while reducing SHE. Our empirical analysis shows that, STIFF is able to maintain a stable frequency of 3.7GHz of the cores with a small standard deviation of 0.23, while maintaining a safe temperature during execution, and it outperforms a state-of-the-art DVFS technique for the FinFET based cores. STIFF also maintains a stable access time at the local L1 caches, while ensuring thermal safety by introducing a cache access cognizant scaling of the supply voltage of the individual local L1 cache-banks without any noticeable performance-loss.