Nested Loop Radio Frequency Synthesizers

This thesis describes how PLL frequency synthesizers with cascaded and nested loop topologies can be used for the synthesis of low noise high frequency signals. Briefly explained, synthesizers with cascaded/nested loops combines a broadband PLL and a narrowband PLL. The broadband PLL makes it possible to obtain a low phase noise even from a relatively noisy VCO with an integrated resonator. The narrowband PLL, on the other hand, makes it possible to tune the output signal with a high frequency resolution. A necessary building block of this kind of synthesizer is a low frequency VCO having low noise. The thesis describes how this kind of VCO could be implemented by the use of low loss external resonator components and by employing tank enhancement for additional noise suppression. Tank enhancement is obtained by the use of centre tapped capacitors in order to reduce the tank impedance. A consequence of tank enhancement is that the transconductance of the gain element must be increased. The Clapp oscillator can be regarded as a Colpitts oscillator with enhanced tank. The thesis describes some of the properties of a Clapp oscillator. The oscillator is analysed both according to an idealized model and by a more detailed model small signal diagram including parasitics. The thesis also includes an analysis of oscillator noise due to noise sources in the transistor. Measurements of the phase noise for a few different oscillator configurations indicates that tank enhancement can indeed be used to suppress the phase noise. Attempts to model the oscillator in Agilent ADS does, however, indicate that the combination of simulated currents and postprocessing by the use of an analytical model gives far too pessimistic excess noise factors. The thesis also describes the design and evaluation of two fully integrated VCOs implemented in 0.35 um CMOS. One of the VCOs had an operating frequency around 5.8 GHz. This VCO was also used as a building block of an experimental broadband PLL synthesizer having a target loop bandwidth of 25 MHz. Due to the large variations in VCO gain as a function of frequency, the PLL had a very narrow locking range. Limitations in the measurement setup also made it impossible to evaluate the phase noise performance of the PLL. The other VCO had an operating frequency around 2.4 GHz and was designed with multiple parallel tuning elements. This configuration could be used to reduce the variations and magnitude of the VCO gain and to make the VCO less sensitive to noise from the charge pump or loop filter, while still maintaining a wide frequency tuning range. Another benefit of multiple tuning inputs would be that the variations in feedback tuning voltage could be reduced. This would reduce the mismatch between the source current and sink current of the charge pump and give a reduction of the reference spur level.