Cristin-resultat-ID: 653593
Sist endret: 22. desember 2009, 00:00
Resultat
Poster
2009

Development and characterization of microscale interconnects and packaging for 3-D microsystems

Bidragsytere:
  • He Liu
  • Kaiying Wang
  • Knut E. Aasmundtveit og
  • Nils Høivik

Presentasjon

Navn på arrangementet: NANOMAT Conference 2009
Sted: LIllehammer
Dato fra: 15. juni 2009
Dato til: 19. juni 2009

Om resultatet

Poster
Publiseringsår: 2009

Importkilder

ForskDok-ID: r09023099

Beskrivelse Beskrivelse

Tittel

Development and characterization of microscale interconnects and packaging for 3-D microsystems

Sammendrag

Packaging of Microsystems is as important as, if not more than, the chip itself. In fact, 50% or more of the total cost of a final product is usually spent on the packaging. Traditionally, 2-D packaging scheme is utilized; sensor die and ASIC are attached to the substrate (typically lead frame) respectively. Electrical connections among MEMS, ASIC and substrate are realized by wire bonds (or other connection methods). In the trend of size shrinking and cost reduction of micro electrical component, the packaging technique can be optimized by means of 3D integration. 3-D integration is an evolving technology for MEMS packaging. In a 3-D package, sensor die and ASIC are stacked to reduce the size of the final product, and shorten the signal path. High I/O density is also allowed. Therefore the cost can be reduced and the performance of MEMS sensor can be optimized the same time. Furthermore, it is possible to combine the stacking process with the cavity sealing process, i.e., one can make the electric connection, mechanical attachment, and cavity sealing process within a single chip stacking step, while traditionally, cavity sealing is a separated process, which is usually done by wafer bonding (usually fairly high temperature and pressure). Therefore, with 3-D stacking, time and cost can be saved, and performance of the product can be improved. In this project, a soldering technique, Solid Liquid InterDiffusion(SLID) with Cu and Sn, is chosen as the interconnection method for 3D stacking. Intermetallic compound (Cu3Sn) can be formed at a lower temperature (250°C~325°C) than its melting point (675°C). Thus once the solder joint is made, it can stand fairly high temperature during the succeeding process, such as molding, 2nd-level packaging, etc. Due to the special nature of the SLID process, it can also stand the process itself repeatedly. The intermetallic Cu3Sn is observed to be quite inert while exposed to moisture, so it is a good candidate material for both interconnects and sealing ring. A series of experiment was done to characterize the material properties of the IMC. Bonding experiments were carried out at different condition, such as temperature, pressure, flux, etc. The IMC formation and bonding quality was investigated by means of shear test, cross-section examination, EDX analysis. Electroplating process is well characterized and especially the uniformity of the electroplated metal (Cu and Sn) is well under control. Moreover, a unique fluxess bonding technique is developed, which is to cover the Cu layer with Cu3Sn intermetalic, which is quite inert to oxidation at elevated temperature, thus no flux is required during the bonding. This project is funded by RCN BIA project No. 174320, "3DHMNS - 3D Heterogeneous Micro Nano Systems".

Bidragsytere

He Liu

  • Tilknyttet:
    Forfatter
    ved Institutt for mikrosystemer ved Universitetet i Sørøst-Norge

Kaiying Wang

  • Tilknyttet:
    Forfatter
    ved Institutt for mikrosystemer ved Universitetet i Sørøst-Norge

Knut Eilif Aasmundtveit

Bidragsyterens navn vises på dette resultatet som Knut E. Aasmundtveit
  • Tilknyttet:
    Forfatter
    ved Institutt for mikrosystemer ved Universitetet i Sørøst-Norge

Nils Deneke Høivik

Bidragsyterens navn vises på dette resultatet som Nils Høivik
  • Tilknyttet:
    Forfatter
    ved Institutt for mikrosystemer ved Universitetet i Sørøst-Norge
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